1. Field of the Invention
The present invention relates to a signal synchronism detecting circuit, and more specifically to a signal synchronism detecting circuit having a serial-to-parallel conversion function of converting an inputted serial data in accordance with a predetermined signal.
2. Description of Related Art
In the prior art, there has been known a signal synchronism detecting circuit for detecting a word synchronism (frame synchronism, byte synchronism) discriminating the boundary or delimiter of bit groups in a time sequence in order to identify the roles of respective bits. In a high speed serial transmission field of a communication system, some of the signal synchronism detecting circuit has a function of receiving a high speed serial data coded by a 8B10B encoder and of executing a serial-to-parallel conversion. The high speed serial data includes a comma signal, which is a delimiter bit group for delimiting data bit groups (each formed of a predetermined number of continuing bits) from each other. The comma signal includes two kinds, namely, xe2x80x9c1100000101xe2x80x9d and its inversion xe2x80x9c0011111010xe2x80x9d. The comma signal is used only at a heading of the word (frame, byte). A receiving side can properly perform the serial-to-parallel conversion by taking the word synchronism on the basis of the comma signal.
Here, a proper serial-to-parallel conversion is that when a received serial signal is serial-to-parallel-converted to restore a parallel signal before the sending, a heading bit of the serial data is correctly recognized, and the parallel signal is restored with no deviation in bit position.
Referring to FIGS. 8A to 8G, a general method for taking the word synchronism in the serial data is diagrammatically illustrated.
Here, consider that as shown in FIG. 8A, for example, two 4-bit parallel signals A1 to A4 and B1 and B4 of 1 Gbps are parallel-to-serial-converted to 4:1 at a sending side, and a serial data of 4 Gbps is received at a receiving side. When the serial data of 4 Gbps is serial-to-parallel-converted to 1:2 to generate two serial data trains, since the serial data of 4 Gbps is continuously received, if the data conversion of 1:2 is performed without taking the word synchronism, two data patterns shown in FIGS. 8B and 8C are obtained. Alternatively, when the serial data of 4 Gbps shown in FIG. 8A is serial-to-parallel-converted to 1:4, since the serial data of 4 Gbps is continuously received, if the data conversion of 1:4 is performed without taking the word synchronism, four data patterns shown in FIGS. 8D, 8E, 8F and 8G are obtained.
For example, if the word synchronism is conducted when the serial data of 4 Gbps shown in FIG. 8A is obtained, when the serial data is converted to the two serial data trains, the serial data is properly converted to the data pattern shown in FIG. 8B. In addition, when the serial data is converted to the four serial data trains, the serial data is properly converted to the data pattern shown in FIG. 8D. If the word synchronism is conducted when the serial data is converted to the two serial data trains of 2 Gbps, it is necessary to detect in which of the two conditions shown in FIGS. 8B and 8C the two serial data trains are. In addition, if the word synchronism is conducted when the serial data is converted to the four serial data trains of 1 Gbps, it is necessary to detect in which of the four conditions shown in FIGS. 8D to 8G the four serial data trains are.
Here, the case of taking the word synchronism for the serial data coded by the 8B10B encoder mentioned above will be described. In a fiber channel or the like, at a sender side, after the serial data is coded by the 8B10B encoder, the data is transmitted. At a receiving side, the word synchronism is taken in order to properly perform the serial-to-parallel conversion on the basis of the received serial data. In the serial data coded by the 8B10B encoding, the number of the same continuing bits (namely, continuing 0s or continuing 1s) is limited to 4 bits at maximum. Only one existing 5-bit signal formed of the same bits is 5 continuing 0s or 1s included in the comma signal.
FIGS. 9A to 9F diagrammatically illustrate how the word synchronism is taken on the basis of the comma signal. When two kinds of comma signal shown in of FIGS. 9A and 9B are received as the serial data of 4 Gbps, if the word synchronism is taken in the condition of 4 Gbps, it is sufficient if the above mentioned two kinds of bit group are detected. However, if the serial data is converted to two serial data trains without taking the word synchronism in the condition of 4 Gbps, the comma signal assumes four different patterns constituted by the two converted serial data trains of 2 Gbps, as shown in FIGS. 9C, 9D, 9E and 9F. Namely, if the word synchronism is taken in the condition of 2 Gbps, it is necessary to detect the word synchronism from the four different converted serial data train patterns.
Referring to FIG. 10, there is shown a circuit diagram of a prior art signal synchronism detecting circuit for the 4 Gbps serial data. The shown signal synchronism detecting circuit includes a 1/10 frequency dividing counter 21 receiving a clock signal of 4 Gbps, a serial-to-parallel converter section 22 and a data input section 23 formed of flipflops F/F-0 to F/F-9. In the word synchronous circuit having this construction, if the 4 Gbps serial data is inputted to the data input section 23, the word synchronism is taken by using the clock signal of 4 Gbps, and the serial-to-parallel conversion of 1:10 is performed to output a 10-bit parallel signal of 400 Mbps. Incidentally, xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d in FIG. 10 indicate the comma signal.
Referring to FIG. 11, there is shown a circuit diagram of a prior art signal synchronism detecting circuit for the 2 Gbps serial data. The shown signal synchronism detecting circuit includes a data input section 24, a 1/5 frequency dividing counter 26, and a serial-to-parallel converter section 27. The data input section 24 includes a converter section 25 for conducting a 1:2 data conversion for the received 4 Gbps serial data, so as to generate two serial data trains of 2 Gbps. In the word synchronous circuit having this construction, after the received 4 Gbps serial data is converted to the two serial data trains of 2 Gbps, the word synchronism is taken, and the serial-to-parallel conversion of 2:10 is performed to output a 10-bit parallel signal of 400 Mbps.
As mentioned above, if the signal synchronism such as the word synchronism is taken in the condition having a high bit rate, the number of patterns to be detected is small, and therefore, the circuit scale is small and the power consumption is low. In addition, since the clock frequency for operating the circuit to detect the signal synchronism is high, the data transfer delay occurring in the signal synchronism is small, and the latency of the overall system is small. However, since the synchronism is detected at the high bit rate, high speed operating circuits and devices become necessary. In addition, since it is necessary to distribute the high speed clock, there is possibility that a clock skew occurs between various circuit blocks. Therefore, there is a troublesome in cautiously distributing the high speed clock.
On the other hand, in the case that the signal synchronism is taken after the data conversion is conducted to lower the bit rate, the high speed operating circuits and devices become unnecessary, and correspondingly, since it also becomes unnecessary to distribute the high speed clock, there is no possibility of a clock skew. However, if the signal synchronism is taken after the bit rate is lowered, the number of patterns to be detected increases, and the scale of the circuit required for the synchronism detection correspondingly becomes large. Furthermore, since the clock frequency for operating the circuit to detect the signal synchronism is low, the data transfer delay occurring in the word synchronism becomes large, and the latency of the overall system also becomes large.
Accordingly, it is an object of the present invention to provide a signal synchronism detecting circuit which has overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a signal synchronism detecting circuit having a relatively small circuit scale and capable of surely performing the serial-to-parallel conversion with a minimized data transfer delay in the synchronism detection and with a reduced power consumption.
The above and other objects of the present invention are achieved in accordance with the present invention by a signal synchronism detecting circuit comprising:
a receiving means receiving a serial data including data bit groups each composed of a predetermined number of continuing bits and delimiter bit groups each composed of a predetermined number of continuing bits for delimiting the data bit groups from one another;
a detecting means for obtaining an exclusive OR between continuing bits of the received serial data, so as to detect the delimiter bit group; and
a serial-to-parallel converting means for serial-to-parallel converting the received serial data on the basis of the result of the detection of the delimiter bit group by the detecting means.
With the above mentioned arrangement, when the signal synchronism detection is conducted for the received serial data, the signal synchronism detection can be precisely conducted by only obtaining the exclusive OR between continuing bits of the received serial data. Therefore, the data transfer delay in the synchronism detection can be minimized and the power consumption can be reduced.
Preferably, the detecting means includes a plurality of exclusive-OR circuits each for obtaining an exclusive OR between one different pair of adjacent bits of the received serial data, a discriminating circuit receiving an output of each of the exclusive-OR circuits for discriminating whether or not the delimiter bit group exists, and a frequency dividing counter for outputting a timing signal to the serial-to-parallel converting means when the discriminating circuit detects the delimiter bit group. In this case, the signal synchronism detecting circuit can be constructed with a very simple circuit structure.
In a specific embodiment, the plurality of exclusive-OR circuits respectively obtain an exclusive OR between a different pair of adjacent bits of five continuing bits of the received serial data, so as to output continuing 0s of four bits when continuing 1s or 0s of five bits appear in the received serial data, and the discriminating circuit includes a logic circuit for outputting a trigger signal to the frequency dividing counter when the discriminating circuit receives the continuing 0s of four bits.
According to another aspect of the present invention, there is provided a signal synchronism detecting circuit comprising:
a receiving means receiving a serial data including data bit groups each composed of a predetermined number of continuing bits and delimiter bit groups each composed of a predetermined number of continuing bits for delimiting the data bit groups from one another;
a first converting means for alternately distributing continuing bits of the received serial data to generate two converted serial data trains;
a first detecting means for obtaining an exclusive OR between continuing bits spread over the two converted serial data trains, so as to detect special bits included in the delimiter bit group and selected from the group consisting of a plurality of continuing 0s and a plurality of continuing 1s;
a second detecting means for obtaining an exclusive OR between two bits which are composed of a bit just before the special bits in a bit transmission direction and a bit just after the special bits in the bit transmission direction, so as to detect whether or not the two bits are a combination of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d;
a third detecting means for obtaining an exclusive OR between two bits which are composed of the bit just before the special bits in a bit transmission direction and a bit before the special bits by two bits in the bit transmission direction, so as to detect a heading bit of the continuing bits spread over the two converted serial data trains; and
a serial-to-parallel converting means for serial-to-parallel converting the two converted serial data trains on the basis of the result of the detection of the first, second and third detecting means.
With the above mentioned arrangement, the signal synchronism is detected after the transfer rate of the received serial data is lowered, but the circuit scale is not enlarged. In addition, the signal synchronism can be detected with a simple construction which only obtains the exclusive-OR between predetermined bits in the converted serial data trains. Therefore, the data transfer delay in the synchronism detection can be minimized and the power consumption can be reduced.
Preferably, the first detecting means includes three exclusive-OR circuits each for obtaining an exclusive OR between one different pair of adjacent bits of four continuing bits spread over the two converted serial data trains. The second detecting means includes one exclusive-OR circuit for obtaining an exclusive OR between two bits which are composed of a bit just before the four continuing bits in a bit transmission direction and a bit just after the four continuing bits in the bit transmission direction. The third detecting means includes one exclusive-OR circuit for obtaining an exclusive OR between two bits which are composed of the bit just before the four continuing bits in a bit transmission direction and a bit before the four continuing bits by two bits in the bit transmission direction. In this case, the signal synchronism detecting circuit can be constructed with a very simple circuit structure.
Here, it should be understood that the exclusive-OR in the present invention includes an exclusive-NOR because the exclusive-NOR is a simple logical inversion of the output of the exclusive-OR.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.